Figure 14-6 on page 14-41 shows a state diagram for the DSP’s clock modes. Note the following key points that this diagram illustrates:
• The MSELx pins provide input for the reset configuration (at reset).
• The MSELx bits in the PLLCTL register provide input when the DSP is in Bypass or Powerdown PLL modes (at runtime).
Figure 14-5. MSELx, BYPASS, and DF Timing
MSEL6–0 BYPA SS DF RESET
tM S H
tP FD
tMS D
tMSS
Managing DSP Clocks
• The PWDN, PLL_OFF, STOPCK, STOPALL, and BYPASS bits in the PLLCTL register control movement between clock modes.
• The PLL determines the mode change from the bits and the bits’
priorities.
These modes are provided in the DSP in order to cutoff clock signals to the core and/or to the peripherals. This is an important requirement for the low-cost power sensitive applications.
In Powerdown All mode both BYPASS and PLL are off, and there are no output clocks. An asynchronous wake-up (FIO_WAKEUP,
TMR_WAKE0, TMR_WAKE1 or TMR_WAKE2) is expected to trigger the wake-up sequence.
In Idle mode the PLL is on, but CCLK is off and/or HCLK, too. An asyn- chronous wake-up or in the case the HCLK is running, an interrupt (IRQ_INT) can trigger the wake-up sequence.
The PLL can be in five different transition states, as specified by the bits in the PLLCTL register.
• Clock Multiplier Mode. BYPASS is off and PLL is on. The output clock is generated by the PLL with the desired frequency ratio.
While in clock multiplier mode, the PLLCTL register’s STOPCK, STO-
PALL, BYPASS, PDWN, DIV2, and IOSEL bits can be changed; the other bits of the PLLCTL register cannot be changed in clock multiplier mode. If more than one of these bits is updated, there is a predefined order for the update, as shown in the state diagram. Any change of these bits leads to a state transition.
• Bypass Mode. BYPASS and PLL are both on. The PLL is in BYPASS mode, and the input clock is directly used to generate the clocks for the core and the peripherals. In this mode the multiplica- tion ratio can be changed. The lock counter defines when the PLL is locked to the new ratio and can get to clock multiplier mode.
While in Bypass mode, the PLLCTL register’s STOPCK, STOPALL,
Figure 14-6. Clock PLL Modes Flowchart
3
Powerdown All Mode
(CC LK= 0, HCLK =0)
Powerdown PLL Mode
(CCL K=C LKIN)
Bypass Mode
(CCL K=C LKIN)
Clock Multiplier Mode
(CCLK=NxCLKIN) PD WN=1
ST O PCK = 1 ST O P A L L = 1
ST O PCK = 1 or ST O P A L L = 1
BYPASS=1
BYPASS=0
ST O PCK= 1 or ST O P AL L = 1
PDWN =1
Idle Mode
(ST OPCK=1⇒⇒⇒⇒CCLK =0) (ST OPA LL = 1⇒⇒⇒⇒C / HCL K= 0 )
MSEL x
Chan ge M SEL x = n e w PL L _ OF F = 0 BYPASS=1
M SEL x = n e w PL L _ O F F = 0 BYPASS=0
Reset Configuration
PL L _ OF F = 0 PL L _ O F F = 1
3
Wake Up Event Wake Up
Event
2 2
1 1
Wake Up Event
1
Wake Up Event
PD WN =1
4 2
MSEL x Chan ge
Notes:
1) A Wake Up Event i s a n i n t e rrru p t t h a t p ro mp t s t h e DSP t o re t urn fro m I d le o r Po w e rd ow n A ll M o d e .
2) Th e PLL mode arbitration priority ( n u mb e r t a gs o n o u tb o un d pa t h s f ro m ea c h mo de ) de t e rmi ne th e mo d e c h a n g e . I f t h e D SP is i n By p a s s mo d e an d b o t h t h e PD W N a n d PL L _ O F F b i ts w h e re s e t in th e s a me c y cl e (f o r ex a mp l e ), t he PLL p ut s th e DSP in Po w e rd o w n A l l mo de b ec a u se t ha t mo d e ch a n g e h a s t h e h ig h e r p rio ri t y ( 1) .
Managing DSP Clocks
PLLOFF, BYPASS, IOSEL, and PDWN bits can be written. The DIV2,
MSEL, and DF bits can also be written when BYPASS=1. If more than one of these bits is updated, there is a predefined order for the update, as shown in Figure 14-6 on page 14-41.
• Idle Mode. The PLL is on, and the core is in Idle mode. The PLLCTL register cannot be written when in Idle mode. An external event or some peripheral activity is expected to generate the wake-up inter- rupt. There are two configurations for this mode; only CCLK may be turned off, or both CCLK and HCLK may be turned off. The PLLCTL register’s BYPASS bit determines the next state of the PLL after wake-up: BYPASS=1 means the next state will be Bypass mode, oth- erwise the next state will be multiplier mode.
• Powerdown PLL Mode. BYPASS is on and PLL is off. The DSP is in Bypass mode, and the input clock is directly used to generate the clocks for the core and the peripherals. In this mode the multiplica- tion ratio (MSEL) can be changed. The lock counter defines when the PLL is locked to the new ratio and can transition to the Bypass mode before switching to multiplier mode. While in powerdown PLL mode, the PLLCTL register’s PDWN, PLLOFF, DF, DIV2, and IOSEL bits can be changed; the BYPASS bit cannot be changed. When the
STOPCK and STOPALL bits change, the next state will be Powerdown mode.
• Powerdown All Mode. The PLL is off, and the output clocks CCLK and HCLK are off. Because the clocks are off, the PLLCTL register state cannot change in this mode. An asynchronous event is expected to trigger the wake-up sequence for the DSP. The PLLOFF bit of the
PLLCTL register determines the next state of the PLL after wake-up:
PLLOFF=0 means the next state will be powerdown PLL mode; oth- erwise the next state will be Bypass mode. If the PLL was in multiply mode before it went into powerdown all mode, it will wake up in Bypass mode but will transition to multiplier mode as soon as the PLL is locked.