The PFx flags on the ADSP-2191 are programmed with a group of flag configuration registers: the Flag Direction register (DIR), the Flag Control registers (FLAGC and FLAGS), the Flag Interrupt Mask Registers (MASKAC,
MASKAS, MASKBC, and MASKBS), the Flag Interrupt Polarity register (FSPR), and the Flag Sensitivity registers (FSSR and FSBER). These registers are described in the following sections.
Several precautions should be observed when programming these flag con- figuration registers:
• To avoid unwanted interrupts, software should only change a
FLAGx[n] bit while its respective interrupt bit, MASKx[n], is masked.
• Five NOPs or instructions must follow an FSPRx[n] bit change, and the respective FLAG[n] bit must be cleared before its interrupt bit is unmasked.
• At reset, all flag configuration registers are initialized to zero; all flag pins are configured as level-sensitive inputs with no inversion, all flag interrupts are masked, and all interrupts are disabled.
• Narrow positive active input [n] pulses are only detectable if
FSPRx[n]=0; narrow negative active input [n] pulses are only detect- able if FSPRx[n]=1.
For more information about the programmable flag registers, see
“ADSP-2191 DSP I/O Registers” on page B-1.
Flag Direction (DIR) Register
The Flag Direction register configures a flag pin as an input or output.
The DIR register is located at I/O memory page 0x06, I/O address 0x000. (The DIR register is also aliased to I/O memory page 0x06, I/O address
0x001.) Writing a “1” to a bit of the DIR register (at either I/O address) configures the corresponding flag pin as an output; writing a “0” config-
ures the corresponding flag pin as an input. Each bit of the DIR register corresponds with each of the 16 available flag pins of the ADSP-2191.
Flag Control (FLAGC and FLAGS) Registers The Flag Control registers set or clear a flag pin.
The Flag Clear register (FLAGC) is used to clear the flag pin when it is con- figured as either an input or an output. FLAGC is located at I/O memory page 0x06, I/O address 0x0002. Writing a “1” to the FLAGC register clears the corresponding flag pin; writing a “0” has no effect on the value of the flag pin. The 16 bits of the FLAGC register correspond to the 16 available flag pins of the ADSP-2191.
The Flag Set register (FLAGS) is used to set the flag pin when it is config- ured as either an input or an output. Setting a flag pin that is configured as an input allows for software configurable interrupts. FLAGS is located at I/O memory page 0x06, I/O address 0x0003. Writing a “1” to the FLAGS register sets the corresponding flag pin; writing a “0” has no effect on the value of the flag pin. The 16 bits of the FLAGS register correspond to the 16 available flag pins of the ADSP-2191.
Flag Interrupt Mask (MASKAC, MASKAS, MASKBC, and MASKBS) Registers
The Flag Interrupt Mask registers enable a flag pin as an interrupt source.
The flag pin can be configured as either an input or an output signal. The
MASKA and MASKB registers allow for two different Programmable Flag 0 and 1 interrupt priority levels for all of the flag pins.
The Flag Interrupt MASKA and MASKB Set registers (MASKAS and MASKBS, respectively) are used to “unmask” or enable the servicing of the flag inter- rupt. The MASKAS register is located at I/O memory page 0x06, I/O address
0x005. The MASKBS register is located at I/O memory page 0x06, I/O address 0x007. Writing a “1” to the MASKAS or MASKBS register unmasks the interrupt capability of the corresponding flag pin; writing a “0” has no
Using Programmable Flags
effect on the masking of the flag pin. The 16 bits of the MASKAS and
MASKBS registers correspond to the 16 available flag pins of the ADSP-2191.
The Flag Interrupt MASKA and MASKB Clear registers (MASKAC and MASKBC, respectively) are used to “mask” or disable the servicing of the flag inter- rupt. The MASKAC register is located at I/O memory page 0x06, I/O address
0x004. The MASKBC register is located at I/O memory page 0x06, I/O address 0x006. Writing a “1” to the MASKAC or MASKBC register masks the interrupt capability of the corresponding flag pin; writing a “0” has no effect on the masking of the flag pin. The 16 bits of the MASKAC and
MASKBC registers correspond to the 16 available flag pins of the ADSP-2191.
Flag Interrupt Polarity (FSPR) Register
The Flag Interrupt Polarity register selects either a high or low polarity of an interrupt signal. Note that the flag polarity applies for input flag pins only (DIR[n]=0).
The Flag Interrupt Polarity register (FSPR) is located at I/O memory page
0x06, I/O address 0x008. (The FSPR register is also aliased to I/O memory page 0x06, I/O address 0x009.) Writing a “0” to a bit of the FSPR register configures the corresponding flag pin as an active high input signal; writ- ing a “1” configures the corresponding flag pin as an active low input signal. The 16 bits of the FSPR register correspond to the 16 available flag pins of the ADSP-2191.
Flag Sensitivity (FSSR and FSBER) Registers
The Flag Sensitivity register determines edge- or level-sensitivity when the flag pin is configured as an input (DIR[n]=0). If the flag pin is configured for edge-sensitivity, the FSSR register also specifies the flag pin’s sensitivity for rising edge, falling edge, or both edges.
FSSR is located at I/O memory page 0x06, I/O address 0x00A. (The FSSR register is also aliased to I/O memory page 0x06, I/O address 0x00B.) Writing a “0” to a bit of the FSSR register configures the corresponding flag pin as a level sensitive input; writing a “1” configures the correspond- ing flag pin as an edge sensitive input. The 16 bits of the FSSR register correspond to the 16 available flag pins of the ADSP-2191.
The Flag Sensitivity Both Edges register (FSBER) is used to configure the sensitivity of the flag pin for either rising- or falling-edge sensitivity (depending on the value of the FSPR[n] bit) or for both-edge sensitivity.
FSBER is located at I/O memory page 0x06, I/O address 0x00C. (The FSBER register is also aliased to I/O memory page 0x06, I/O address 0x00D.) Writing a “0” to a bit of the FSBER register configures the corresponding flag pin for either rising-edge or falling-edge sensitivity (as determined by the value of the corresponding bit of the FSPR register); writing a “1” con- figures the corresponding flag pin for both-edges sensitivity. The 16 bits of the FSBER register correspond to the 16 available flag pins of the ADSP-2191.
For more information, see “Programmable Flags Example” on page 14-54.