• Nem Talált Eredményt

To show the feasibility of the proposed inverter topology, a hardware setup of 9-level symmetrical topology is considered. The experimental setup consists of two basic blocks connected in series with each block consists of two DC sources with equal magnitude as 16V. A rectifier unit with an isolation transformer and a capacitor filter forms the DC voltage sources. The diode IN4007 acts as a bridge rectifier unit. To get the constant voltage to the controller, IC7805 acts as a voltage regulator. The gate signals for driving the power switches has been generated with the help of 16-bit digital signal controller dsPIC30F2010. As seen from Table 5, the switches S21 and S22 were neglected and therefore 10 MOSFET (IRF840N) power switches were employed in the hardware setup. Fig. 19 shows the experimental results for the symmetric 9-level inverter. It is observed that the THD of the 9-level output waveform is achieved as 11%.

(a)

(b) Figure 19

Hardware results (a) 9-level Output Voltage and (b) THD

Conclusions

In this paper, a new topology of a symmetrical and asymmetrical type, multilevel inverter, with reduced switch count, is proposed. Different algorithms for the determination of the magnitude of the DC voltage sources are analyzed. The comparative analysis of the proposed inverter topology with other recent topologies show that the proposed topology significantly reduces the number of DC voltage sources and power switches. The advantages of the proposed topology include simple construction, ease of control, a reduced number of components, lower THD and a minimized cost. The number of on-state switches in the conduction path, are also reduced, as compared with other existing topologies. The performance of the proposed inverter topology is analyzed for 9-level symmetrical and 31-level asymmetrical cases. Finally, the feasibility of the proposed inverter

topology for 9-level symmetrical operation has been tested experimentally. The experimental results are in good agreement with the simulation results.

Acknowledgements

This research work was supported and funded by SSN Trust.

References

[1] S. H. Ashan and M. Monfared: Design and comparison of nine-level single-phase inverters with a pair of coupled inductors and two dc sources, IET Power Electronics, Vol. 9, No. 11, pp. 2271-2281, 2016

[2] S. H. Ashan and M. Monfared: Generalised single-phase N-level voltage-source inverter with coupled inductors, IET Power Electronics, Vol. 8, No.

11, pp. 2257-2264, 2015

[3] E. Zamiri, N. Vosoughi, S. H. Hosseini, R. Barzegarkhoo and M. Sabahi: A New Cascaded Switched-Capacitor Multilevel Inverter Based on Improved Series–Parallel Conversion With Less Number of Components, IEEE Transactions on Industrial Electronics, Vol. 63, No. 6, pp. 3582-3594, 2016 [4] A. Nabae, I. Takahashi and H. Akagi: A New Neutral-Point-Clamped PWM Inverter, IEEE Transactions on Industry Applications, Vol. IA-17, No. 5, pp. 518-523, 1981

[5] J. Rodriguez, S. Bernet, P. K. Steimer and I. E. Lizama: A Survey on Neutral-Point-Clamped Inverters, IEEE Transactions on Industrial Electronics, Vol. 57, No. 7, pp. 2219-2230, 2010

[6] C. Feng, J. Liang and V. G. Agelidis: Modified Phase-Shifted PWM Control for Flying Capacitor Multilevel Converters, IEEE Transactions on Power Electronics, Vol. 22, No. 1, pp. 178-185, 2007

[7] T. A. Meynard, H. Foch, F. Forest, C. Turpin, F.Richardeau, L.Delmas, G.

Gateau and E. Lefeuvre: Multicell converters: derived topologies, IEEE Transactions on Industrial Electronics, Vol. 49, No. 5, pp. 978-987, 2002 [8] F. Z. Peng and J. S. Lai: Multilevel cascade voltage source inverter with

separate DC sources, U.S. Patent 5 642 275, 1997

[9] K. K. Gupta, A. Ranjan, P. Bhatnagar, L. K. Sahu and S. Jain: Multilevel Inverter Topologies With Reduced Device Count: A Review, IEEE Transactions on Power Electronics, Vol. 31, No. 1, pp. 135-151, 2016 [10] S. P. Gautam, L. Kumar and S. Gupta: Hybrid topology of symmetrical

multilevel inverter using less number of devices, IET Power Electronics, Vol. 8, No. 11, pp. 2125-2135, 2015

[11] K. K. Gupta and S. Jain: Topology for multilevel inverters to attain maximum number of levels from given DC sources, IET Power Electronics, Vol. 5, No. 4, pp. 435-446, 2012

[12] P. Lezana, J. Rodriguez and D. A. Oyarzun: Cascaded Multilevel Inverter With Regeneration Capability and Reduced Number of Switches, IEEE Transactions on Industrial Electronics, Vol. 55, No. 3, pp. 1059-1066, 2008 [13] M. F. Kangarlu, E. Babaei and S. Laali: Symmetric multilevel inverter with reduced components based on non-insulated dc voltage sources, IET Power Electronics, Vol. 5, No. 5, pp. 571-581, 2012

[14] C. I. Odeh and D. B. N. Nnadi: Single-phase 9-level hybridised cascaded multilevel inverter, IET Power Electronics, Vol. 6, No. 3, pp. 468-477, 2013

[15] E. S. Najmi and A. Ajami: Modular symmetric and asymmetric reduced count switch multilevel current source inverter, IET Power Electronics, Vol. 9, No. 1, pp. 51-61, 2016

[16] H. P. Vemuganti, D. Sreenivasarao and G. Siva Kumar: Improved pulse-width modulation scheme for T-type multilevel inverter, IET Power Electronics, Vol. 10, No. 8, pp. 968-976, 2017

[17] M. Kaliamoorthy, V. Rajasekaran, I. G. Christopher Raj and L. Hubert Tony Raj: Generalised hybrid switching topology for a single-phase modular multilevel inverter, IET Power Electronics, Vol. 7, No. 10, pp.

2472-2485, 2014

[18] A. Farakhor, R. R. Ahrabi, H. Ardi and S. N. Ravadanegh: Symmetric and asymmetric transformer based cascaded multilevel inverter with minimum number of components, IET Power Electronics, Vol. 8, No. 6, pp. 1052-1060, 2015

[19] E. Babaei, S. H. Hosseini, G. B. Gharehpetian, M. T. Haque, M. Sabahi:

Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology, Electric Power Systems Research, Vol.

77, pp. 1073-1085, 2007

[20] A. Mokhberdoran and A. Ajami: Symmetric and Asymmetric Design and Implementation of New Cascaded Multilevel Inverter Topology, IEEE Transactions on Power Electronics, Vol. 29, No. 12, pp. 6712-6724, 2014 [21] G. S. Perantzakis, F. H. Xepapas and S. N. Manias: A Novel Four-Level

Voltage Source Inverter—Influence of Switching Strategies on the Distribution of Power Losses, IEEE Transactions on Power Electronics, Vol. 22, No. 1, pp. 149-159, 2007

[22] M. R. J. Oskuee, E. Salary and S. N. Ravadanegh: Creative design of symmetric multilevel converter to enhance the circuit's performance, IET Power Electronics, Vol. 8, No. 1, pp. 96-102, 2015

[23] M. Jayabalan, B. Jeevarathinam and T. Sandirasegarane: Reduced switch count pulse width modulated multilevel inverter, IET Power Electronics, Vol. 10, No. 1, pp. 10-17, 2017

[24] E. Babaei: A Cascade Multilevel Converter Topology With Reduced Number of Switches, IEEE Transactions on Power Electronics, Vol. 23, No. 6, pp. 2657-2664, 2008

[25] E. Babaei, S. Laali and S. Alilu: Cascaded Multilevel Inverter With Series Connection of Novel H-Bridge Basic Units, IEEE Transactions on Industrial Electronics, Vol. 61, No. 12, pp. 6664-6671, 2014

[26] M. R. Banaei, M. R. J. Oskuee and H. Khounjahan: Reconfiguration of semi-cascaded multilevel inverter to improve systems performance parameters, IET Power Electronics, Vol. 7, No. 5, pp. 1106-1112, 2014 [27] M. R. Banaei and E. Salary: Verification of New Family for Cascade

Multilevel Inverters with Reduction of Components, Journal of Electrical Engineering and Technology, Vol. 6, No. 2, pp. 245-254, 2011

[28] E. Babaei, S. H. Hosseini: New cascaded multilevel inverter topology with minimum number of switches, Energy Conversion and Management, Vol.

50, pp. 2761-2767, 2009

[29] A. Ajami, M. R. J. Oskuee, A. Mokhberdoran and A. Van den Bossche:

Developed cascaded multilevel inverter topology to minimise the number of circuit devices and voltage stresses of switches, IET Power Electronics, Vol. 7, No. 2, pp. 459-466, 2014

[30] B. P. McGrath and D. G. Holmes: Multicarrier PWM strategies for multilevel inverters, IEEE Transactions on Industrial Electronics, Vol. 49, No. 4, pp. 858-867, 2002

[31] H. Lou, C. Mao, D. Wang, J. Lu and L. Wang: Fundamental modulation strategy with selective harmonic elimination for multilevel inverters, IET Power Electronics, Vol. 7, No. 8, pp. 2173-2181, 2014

[32] O. Lopez, J. Alvarez, J. D. Gandoy and F. D. Freijedo: Multilevel Multiphase Space Vector PWM Algorithm, IEEE Transactions on Industrial Electronics, Vol. 55, No. 5, pp. 1933-1942, 2008

[33] Z. Du, L. M. Tolbert and J. N. Chiasson: Active harmonic elimination for multilevel converters, IEEE Transactions on Power Electronics, Vol. 21, No. 2, pp. 459-469, 2006

[34] R. S. Alishah, S. H. Hosseini, E. Babaei and M. Sabahi: Optimal Design of New Cascaded Switch-Ladder Multilevel Inverter Structure, IEEE Transactions on Industrial Electronics, Vol. 64, No. 3, pp. 2072-2080, 2017 [35] S. F. Ahmed, C. F. Azim, H. Desa and A. S. T. Hussain: Model Predictive Controller-based, Single Phase Pulse Width Modulation (PWM) Inverter for UPS Systems, Acta Polytechnica Hungarica, Vol. 11, No. 6, pp. 23-38, 2014

[36] V. Thiyagarajan and P. Somasundaram: Modeling and Analysis of Novel

Components, CMES: Computer Modeling in Engineering and Sciences, Vol. 113, No. 4, pp. 461-473, 2017

[37] I. Vajda, Y. N. Dementyev, K. N. Negodin, N. V. Kojain, L. S. Udut, I. А.

Chesnokova: Limiting Static and Dynamic Characteristics of an Induction Motor under Frequency Vector Control, Acta Polytechnica Hungarica, Vol.

14, No. 6, pp.7-27, 2017

[38] V. Thiyagarajan and P. Somasundaram: Analysis of Multicarrier PWM techniques for Photovoltaic fed Cascaded H-Bridge Multilevel Inverter, Journal of Electrical and Electronics Engineering, Vol. 10, No. 1, pp. 85-90, 2017

[39] K. Boora and J. Kumar: General topology for asymmetrical multilevel inverter with reduced number of switches, IET Power Electronics, Vol. 10, No. 15, pp. 2034-2041, 2017

[40] M. Saeedian, J. Adabi and S. M. Hosseini: Cascaded multilevel inverter based on symmetric–asymmetric DC sources with reduced number of components, IET Power Electronics, Vol. 10, No. 12, pp. 1468-1478, 2017 [41] P. L. Kamani and M. A. Mulla: Middle-Level SHE Pulse-Amplitude Modulation for Cascaded Multilevel Inverters, IEEE Transactions on Industrial Electronics, Vol. 65, No. 3, pp. 2828-2833, 2018

[42] B. Kirankumar, Y. V. Siva Reddy and M. Vijayakumar: Multilevel inverter with space vector modulation: intelligence direct torque control of induction motor, IET Power Electronics, Vol. 10, No. 10, pp. 1129-1137, 2017

[43] S. K. Sahoo and T. Bhattacharya: Phase-Shifted Carrier-Based Synchronized Sinusoidal PWM Techniques for a Cascaded H-Bridge Multilevel Inverter, IEEE Transactions on Power Electronics, Vol. 33, No.

1, pp. 513-524, 2018

[44] J. S. Hu, J. N. Lin and H. C. Chen: A Discontinuous Space Vector PWM Algorithm in abc Reference Frame for Multilevel Three-Phase Cascaded H-Bridge Voltage Source Inverters, IEEE Transactions on Industrial Electronics, Vol. 64, No. 11, pp. 8406-8414, 2017

[45] N. Arun and M. M. Noel: Crisscross switched multilevel inverter using cascaded semi-half-bridge cells, IET Power Electronics, Vol. 11, No. 1, pp.

23-32, 2018

[46] A. Ajami, M. R. J. Oskuee, M. T. Khosroshahi and A. Mokhberdoran:

Cascade-multi-cell multilevel converter with reduced number of switches, IET Power Electronics, Vol. 7, No. 3, pp. 552-558, 2014

[47] F. Chabni, R. Taleb and M. Helaimi: ANN-based SHEPWM using a harmony search on a new multilevel inverter topology, Turkish Journal of

Electrical Engineering and Computer Sciences, Vol. 25, No. 6, pp. 4867-4879, 2017

[48] M. Ramya and P. Usha Rani: Asymmetrical Cascaded Twenty Seven level Inverter based STATCOM, Rev. Roum. Sci. Techn.–Électrotechn.

etÉnerg., Vol. 62, No. 4, pp. 411-416, 2017

[49] R. E. Precup, S. Preitl and P. Korondi: Fuzzy Controllers With Maximum Sensitivity for Servosystems, IEEE Transactions on Industrial Electronics, Vol. 54, No. 3, pp. 1298-1310, 2007

[50] C. Cecati, F. Ciancetta and P. Siano: A Multilevel Inverter for Photovoltaic Systems With Fuzzy Logic Control, IEEE Transactions on Industrial Electronics, Vol. 57, No. 12, pp. 4115-4125, 2010

[51] V. Thiyagarajan and P. Somasundaram: Modified Seven Level Symmetric Inverter with Reduced Switch Count, Advances in Natural and Applied Sciences, Vol. 11, No. 7, pp. 264-271, 2017

[52] F. Chabni, R. Taleb, M. Helaimi: Output voltage waveform improvement of modified cascaded H-bridge multilevel inverter using selective harmonic elimination technique based on hybrid genetic algorithm, Rev. Roum. Sci.

Techn.–Électrotechn. etÉnerg., Vol. 62, No. 4, pp. 405-410, 2017

KAPCSOLÓDÓ DOKUMENTUMOK