Table G-0.
Listing G-0.
Terms
Arithmetic Logic Unit (ALU). This part of a processing element performs arithmetic and logic operations on fixed-point data.
Asynchronous transfers. Asynchronous host accesses of the DSP. After acquiring control of the DSP's external bus, the host must assert the CS pin of the DSP it wants to access.
Base address. The starting address of a circular buffer to which the DAG wraps around. This address is stored in a DAG Bx register.
Base registers. A base (Bx) register is a Data Address Generator (DAG) register that sets up the starting address for a circular buffer.
Bit-reverse addressing. The Data Address Generator (DAG) provides a bit-reversed address during a data move without reversing the stored address.
Boot Memory Space. The DSP supports an external boot EPROM mapped to external memory and selected with the BMS pin. The boot EPROM provides one of the methods for automatically loading a program into the internal memory of the DSP after power-up or after a software reset.
Circular buffer addressing. The DAG uses the Ix, Mx, Lx, and Bx register settings to constrain addressing to a range of addresses. This range con- tains data that the DAG steps through repeatedly, “wrapping around” to
Companding (compressing/expanding). This is the process of logarithmi- cally encoding and decoding data to minimize the number of bits that must be sent.
Conditional branches. These are Jump or Call/return instructions whose execution is based on testing an If condition.
Data Address Generators. The data address generators (DAGs) provide memory addresses when data is transferred between memory and registers.
Data register file. This is the set of data registers that transfer data between the data buses and the computation units. These registers also provide local storage for operands.
Data registers (Dreg). These are registers in the computational units.
These registers are hold operands for multiplier, ALU, or shifter operations.
Delayed branches. These are Jumps and Call/return instructions with the delayed branches (DB) modifier. In delayed branches, two (instead of four) instruction cycles are lost in the pipeline, because the DSP executes the two instructions after the branch while the pipeline fills with instructions from the new branch.
Descriptor (DMA) loading. The process in which the DSP's DMA con- troller downloads a DMA descriptor from data memory and autoinitializes the DMA parameter registers.
Direct branches. These are Jump or Call/return instructions that use an absolute—not changing at runtime—address (such as a program label) or use a PC-relative address.
DMA (Direct Memory Accessing). The DSP’s I/O processor supports DMA of data between DSP memory and external memory, host, or peripherals through the external, host, serial, SPI, and UART ports. Each DMA operation transfers an entire block of data.
DMA chaining. The DSP supports chaining together multiple DMA sequences. In chained DMA, the I/O processor loads the next DMA descriptor (DMA parameters) into the DMA parameter registers when the current DMA finishes and auto-initializes the next DMA sequence.
DMA descriptor registers. These registers hold the setup for a direct memory access process.
DMA descriptor chain loading. This is the process that the I/O processor uses for loading the descriptor of the next DMA sequence into the param- eter registers during chained DMA.
Edge-sensitive interrupt. The DSP detects this type of interrupt if the input signal is high (inactive) on one cycle and low (active) on the next cycle when sampled on the rising edge of CLKIN.
Endian Format, Little Versus Big. The DSP uses big-endian format—
moves data starting with most-significant-bit and finishing with least-sig- nificant-bit—in almost all instances. The two exceptions are bit order for data transfer through the serial port and word order for packing through the external port. For compatibility with little-endian (least-signifi- cant-first) peripherals, the DSP supports both big- and little-endian bit order data transfers. Also for compatibility little endian hosts, the DSP supports both big- and little endian word order data transfers.
External port. This port extends the DSPs internal address and data buses off-chip, providing the processor’s interface to off-chip memory and peripherals.
Flag update. The DSP’s update to status flags occurs at the end of the cycle in which the status is generated and is available on the next cycle.
Harvard architecture. DSPs use memory architectures that have separate buses for program and data storage. The two buses let the DSP get a data word and an instruction simultaneously.
I/O processor. The DSP has a distributed DMA architecture with DMA controllers for each DMA capable peripheral. Also, most ports have some direct (non-DMA) access to internal memory and I/O memory. The term I/O processor refers globally to the DMA controllers, DMA channel arbi- tration, and peripheral-to-bus connections.
I/O processor register. One of the control, status, or data buffer registers of the DSP's on-chip I/O processor.
Idle. An instruction that causes the processor to cease operations, holding its current state until an interrupt occurs. Then, the processor services the interrupt and continues normal execution.
Index registers. An index register is a Data Address Generator (DAG) reg- ister that holds an address and acts as a pointer to memory.
Indirect branches. These are Jump or Call/return instructions that use a dynamic—changes at runtime—address that comes from the PM data address generator.
Interrupts. Subroutines in which a runtime event (not an instruction) triggers the execution of the routine.
JTAG port. This port supports the IEEE standard 1149.1 Joint Test Action Group (JTAG) standard for system test. This standard defines a method for serially scanning the I/O status of each component in a system.
Jumps. Program flow transfers permanently to another part of program memory.
Length registers. A length register is a Data Address Generator (DAG) register that sets up the range of addresses a circular buffer.
Level-sensitive interrupts. The DSP detects this type of interrupt if the signal input is low (active) when sampled on the rising edge of CLKIN.
Loops. One sequence of instructions that executes several times with zero overhead.
Memory blocks and banks. The DSP’s internal memory is divided into blocks that are each associated with different data address generators. The DSP’s external memory spaces is divided into banks, which may be addressed by either data address generator. External memory banks also may be configured for size and access waitstates.
Modified addressing. The DAG generates an address that is incremented by a value or a register.
Modify address. The Data Address Generator (DAG) increments the stored address without performing a data move.
Modify registers. A modify register is a Data Address Generator (DAG) register that provides the increment or step size by which an index register is pre- or post-modified during a register move.
Multifunction computations. Using the many parallel data paths within its computational units, the DSP supports parallel execution of multiple computational instructions. These instructions complete in a single cycle, and they combine parallel operation of the computational units and mem- ory accesses.The multiple operations perform the same as if they were in corresponding single-function computations.
Multiplier. This computational unit does fixed-point multiplication and executes fixed-point multiply/add and multiply/subtract operations.
Peripherals. This refers to everything outside the processor core. The ADSP-2191’s peripherals include internal memory, external port, I/O processor, JTAG port, and any external devices that connect to the DSP.
Precision. The precision of a floating-point number depends on the num- ber of bits after the binary point in the storage format for the number.
Post-modify addressing. The Data Address Generator (DAG) provides an address during a data move and auto-increments the stored address for the next move.
Pre-modify addressing. The Data Address Generator (DAG) provides a modified address during a data move without incrementing the stored address.
Saturation (ALU saturation mode). In this mode, all positive fixed-point overflows return the maximum positive fixed-point number, and all nega- tive overflows return the maximum negative number.
Serial ports. The DSP has three synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal periph- eral devices.
Shifter. This computational unit completes logical shifts and arithmetic shifts on 16-bit operands. Also, the Shifter can derive exponents.
Subroutines. The processor temporarily interrupts sequential flow to exe- cute instructions from another part of program memory.
Time Division Multiplexed (TDM) mode. The serial ports support TDM or multichannel operations. In multichannel mode, each data word of the serial bit stream occupies a separate channel— each word belongs to the next consecutive channel so that, for example, a 24-word block of data contains one word for each of 24 channels.
Descriptor, DMA. A set of DMA parameter register values stored in data memory that are downloaded by the DSP's DMA controller for chained DMA operations.
Tristate Versus Three-state. Analog Devices documentation uses the term
“three-state” instead of “tristate” because Tristate™ is a trademarked term, which is owned by National Semiconductor.
Von Neumann architecture. This is the architecture used by most (non-DSP) microprocessors. This architecture uses a single address and data bus for memory access.
Write-1-to-clear (W1C). When a control or status bit is cleared (=0) through being set (written with a 1), the bit is called W1C. Many “sticky”
bits are W1C.
