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Figure E-19. SYSTAT register bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0
HSTMHost Mastership BSYNBus Synchronization
IDCID Code
CRBMCurrent Bus Master
VIPDVector Interrupt Pending
HPSHost Packing Status 0= fully packed 1= partially packed
SWPDData Pending in Slave Write FIFO
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Table E-26 lists and describes the individual bits of the SYSTAT register:
.Table E-26. SYSTAT register
Bit Name Description 0 HSTM Host mastership.
Indicates whether or not the host processor is the current bus master.
0= bus slave 1= bus master 1 BSYN Bus synchronization.
Indicates whether or not bus arbitration logic is synchronized.
0= unsynchronized 1= synchronized 2-3 Reserved
4-5 CRBM Current bus master.
Identifies the ID code of the ADSP-21065L that is the current bus master.
00= reserved for single-processor systems only 01= processor with ID1
10= processor with ID2 11= reserved
6-7 Reserved
8-9 IDC ID code (ID1-0) of the processor.
Identifies the IDx code of this processor.
00= reserved for single-processor systems only 01= ID1
10= ID2 11= reserved 10-11 Reserved
12 SWPD Slave write pending data.
Indicates whether valid data is pending in the slave write FIFO.
0= No data pending
CLeared after the processor transfers data in the slave write FIFO to the target IOP register.
1= Data pending
Set when the slave write FIFO receives new data.
13 VIPD Vector interrupt pending.
Indicates whether or not a vector interrupt is pending.
0= none pending 1= pending
Table E-26. SYSTAT register (Cont’d)
Bit Name Description
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14 HPS Host packing status.
Indicates the progress of the host access pack-ing procedure.
0= fully packed 1= partially packed 15-31 Reserved
Table E-26. SYSTAT register (Cont’d)
Bit Name Description
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Applications use the WAIT register to set up external memory wait states and the processor’s response to the ACK signal.
For details on using the WAIT register, in ADSP-21065L SHARC User’s Manual see:
• Chapter 5, Memory
• Chapter 6, DMA
• Chapter 7, Multiprocessing
• Chapter 12, System Design In this manual, see:
• Appendix A, Instruction Set Reference
The WAIT register is memory-mapped in internal memory at address
0x0002
.
After reset, the WAIT register is initialized to
0x200D 6B5Aas shown in Figure E-20 on page E-112. This configures the processor for:
• Six internal wait states.
• Dependence on ACK for all external memory banks.
• Multiprocessor memory space wait state enabled
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.
Figure E-20. WAIT register bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 1 0 0 0 0 1 1 0 1 0 1 1 0 1
EB3WS Ext. Mem. Bnk 3
# of Wait States EB3WM (high bit) Ext. Mem. Bnk 3 Wait State Mode MMSWS
Multiprocessor Mem. Space Wait State
HIDMA Handshake Idle Cycle for DMA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 0
EB3WM (low bit) Ext. Mem. Bnk 3 Wait State Mode EB2WS
Ext. Mem. Bnk 2
# of Wait States EB2WM Ext. Mem. Bnk 2 Wait State Mode
EB1WS Ext. Mem. Bnk 1
# of Wait States EB1WM Ext. Mem. Bnk 1 Wait State Mode EB0WM Ext. Mem. Bnk 0 Wait State Mode EB0WS Ext. Mem. Bnk 0
# of Wait States RBWSROM Boot
Wait State
RBWMROM Boot Wait Mode
Table E-27 lists and describes the individual bits of the WAIT register:
.Table E-27. WAIT register
Bit Name Description
0-1 EB0WM External bank 0 wait state mode 00= external acknowledge only (ACK) 01= internal wait states only
10= both internal and external acknowledge required
11= either internal or external acknowledge required
2-4 EB0WS External bank 0 number of wait states.
000=0 wait states; no bus idle cycle1; no hold time cycle2
001=1 wait state; a bus idle cycle; no hold time cycle
010=2 wait states; a bus idle cycle; no hold time cycle
011=3 wait states; a bus idle cycle; no hold time cycle
100=4 wait states; no bus idle cycle; a hold time cycle
101=5 wait states; no bus idle cycle; a hold time cycle
110=6 wait states; a bus idle cycle; no hold time cycle
111=0 wait states; a bus idle cycle; no hold time cycle
5-6 EB1WM External bank 1 wait state mode.
For parameter values, see EB0WM parameter on
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7-9 EB1WS External bank 1 number of wait states.
For parameter values, see EB0WS parameter on page E-113.
10-11 EB2WM External bank 2 wait state mode.
For parameter values, see EB0WM parameter on page E-113.
12-14 EB2WS External bank 2 number of wait states.
For parameter values, see EB0WS parameter on page E-113.
15-16 EB3WM External bank 3 wait state mode.
For parameter values, see EB0WM parameter on page E-113.
17-19 EB3WS External bank 3 number of wait states.
For parameter values, see EB0WS parameter on page E-113.
20-21 RBWM ROM boot wait mode.
Controls the wait mode for accesses that use the BMS pin. See the BSO bit in Table E-25 on page E-101.
For parameter values, see EB0WM parameter on page E-113.
22-24 RBWS ROM boot wait state.
Controls the wait state for accesses that use the BMS pin. See the BSO bit in Table E-25 on page E-101.
For parameter values, see EB0WS parameter on page E-113.
Table E-27. WAIT register (Cont’d)
Bit Name Description
1 Bus idle cycle = an inactive bus cycle the processor automatically generates to avoid bus driving conflicts. For d devices with slow disable time, enable bus idle cycle generation with EBxWS pa-rameter. Does not apply to SDRAM accesses.
2 Hold time cycle = an inactive bus cycle the processor automatically generates at the end of a read
or write operation to provide a longer hold time for address and data. When enabled, the address and data remain unchanged and driven for one cycle after the read or write strobes are deasserted.
Does not apply to SDRAM accesses.
Both the bus idle cycle and the hold time cycle occur if programmed, regardless of the wait state mode. For example, the ACK-only wait state mode can have a hold time cycle programmed for it.
25-28 Reserved
29 HIDMA Handshake idle cycle for DMA.
Single idle cycle for DMA handshake.
30 MMSWS Multiprocessor memory space wait state.
Single wait state for multiprocessor memory space accesses.
31 Reserved
Table E-27. WAIT register (Cont’d)
Bit Name Description