fer method, using a micromanipulator (see Section 3.2.3 and Figure 3.4). To sum up, the steps of the bottom-gated CPSD fabrication were the following.
1. Creating the bottom-gate structure.We define the bottom-gate structure with EBL. In case of the uniform, equidistant bottom-gates (such as on Figure 5.4(b) and (c)), the gate width is 40 nm and the periodicity is 100 nm. The metallic film with 4 nm Ti/18 nm Pt layer structure is e-beam evaporated.
2. Dielectrics deposition. As the insulator over the bottom-gates, ∼25 nm silicon nitride is deposited with PECVD. This step is maskless, the dielectrics is covering the whole wafer.
3. NW placement. Next, we place the InAs NW with the micromanipulator on the wafer, centered over a bottom-gate unit (Figure 3.4).
4. Creating the normal electrodes. We define the normal electrodes with EBL.
The NW oxide layer is removed either by Ar sputter-etching or sulfur passivation (see Section 3.1.3). The metallic layer is e-beam evaporated (7 nm Ti/95 nm Au).
5. Dielectrics removal. To make the bottom-gate accessible for contacting, the di-electrics over them must be partially removed. We define rectangular windows with EBL, and the dielectrics is etched with CHF3/O2 RIE (see Table A.2).
6. Contacting the bottom-gates. In the next EBL cycle, the bottom-gates are contacted with metallic lines, usually with the same layer structure as the normal contacts.
7. Creating the superconducting contact. In the last EBL cycle, the supercon-ducting electrode is defined. The NW oxide is removed similarly as in the case of the normal electrodes (step 4). Niobium (Nb) and lead (Pb) superconducting electrodes were used in the bottom-gated generations, deposited with sputtering and e-beam evaporation, respectively.
Altogether, the fabrication procedure involves 5 EBL cycles. The first two steps can be done in batch production, creating multiple chip templates on a single silicon wafer. In principle, one bottom-gate unit with∼10 local gates can host a single CPSD. However, we have often encountered imperfections. To counterbalance the flawed structures, we have designed each chip template with∼300 bottom-gate units, arranged in a regular grid (see Figure 3.4(d)). Because of instrumental constraints – the limited number of measurement lines –, we produce only two CPSDs per chip.
Optionally, after NW placement (step 3) the NW can be imaged in an SEM, to rule out possible mistakes and prevent further complications. For example, it can happen that two NWs stick together, which cannot be resolved in an optical microscope.5Furthermore, not only the NW, but the bottom-gate unit can be also inspected at this step. In extreme cases, the faulty units can be already identified in the optical image (for example, see
5We remark that the apparent color of the NW usually gives a hint. Single, thin NWs appear yel-lowish and homogeneous in bright field illumination. Thicker, or double NWs are usually darker, and inhomogeneous in color.
Figure 3.4(d), uppermost row, bottom-gate unit in the center). The thin bottom-gate lines might have discontinuities, possibly originating from underdose or resist imperfections, which can render the whole bottom-gate useless. However, because of the presence of the silicon nitride layer, such details are hard to see in the SEM. Alternatively, they can be imaged right away after step 1, before dielectrics deposition, but then a detailed bookkeeping of the chip templates is necessary.
Importantly, we create the normal contacts (step 4) right after NW placement, because they fix the NW on the wafer. Otherwise they may detach in the wet processing steps.
The superconducting contact could be also used for this purpose, but the superconduc-tor material (Nb, Pb) is degrading faster due to oxidation in the ambient environment, to which we expect the CPS to be sensitive. Therefore, we create the superconducting contacts in the last step, and try to minimize the time spent between the fabrication and the measurements. For the same reason, we usually store the finished samples in a high vacuum chamber until it can be loaded into the cryostat.
If sulfur passivation is used for the oxide removal in ohmic contact formation, then contacting the bottom-gates can be done in the step as the creation of the normal elec-trodes. However, if Ar sputter-etching is used, then they must be done separately, as in the listing, because the thin bottom-gate film might become etched completely. In principle the dielectrics removal and bottom-gate contacting could be done in the same step, but the bottom-gate structure, tiled across the whole chip (see Figure 3.4(d)), would make the scheme prone to accidental electrical shorts.
The NW diameter sets a minimum thickness for the metallic layer in case of the deposition of the superconducting and normal contacts. Accordingly, a film thickness of
∼100 nm was chosen. Regarding the superconducting electrodes, while Nb was deposited by sputtering6, Pb was e-beam evaporated. In case of Pb electrodes, in fact a 3-layer sandwich structure was created with 4.5 nm Pd/110 nm Pb/20 nm In. The Pd serves as a sticking layer, the In capping layer protects from oxidation. Pb has a low melting point, and in connection with that, it was empirically found that strong surface diffusion during the film deposition results in ill-defined edges. Therefore, the sample was intensely cooled with liquid nitrogen to around−90◦C for the evaporation. Also, we payed extra attention to evaporate the surface oxide on the Pb source, before we started the deposition on the sample by opening the sample shutter. The removal of the oxide is reflected in the color change of the glow around the source. This deposition procedure was developed by J¨org Gramich (UniBasel) for CNT CPSDs [59].
In this fabrication scheme the bonding pads are not pre-patterned, but created in the same step as the corresponding electrode. Because of this, the bondability must be also considered. For example, the Pb film was empirically found hard to contact with wedge bonding, most probably because Pb is too soft, mechanically. Therefore, the bonding pad for the Pb superconducting electrode must be created from another material, together with the Ti/Au normal electrodes, for example.
6In case of the Nb strips, vertical, or over-folded ridges of excess material can be seen at the edge on Figures 5.4(b) and (c). This feature originates from the filling of the undercut in sputter-deposition.
(a)
(c) (d)
(b)
Figure 5.4: Evolution of the Cooper pair splitter device. Artificially colored SEM pictures of 4 generations. (a) Representative device used in the pioneering works, adopted from [183]. Here an aluminum electrode was used as the source of Cooper pairs, the global back-gate and two top gates were available for the tuning of the electrostatic potential. (b) Device with uniform, equidistant bottom-gates. Silicon nitride was used as the dielectrics, the aluminum superconduc-tor was replaced by niobium. (c) A device with bottom-gates similar to as in (b), but the normal electrodes are placed further apart to reduce the screening of the gates. The synthesis of InAs NWs has been improved parallel to Cooper pair splitters, in this generation the devices were built on top of stacking-fault-free NWs. The experimental results presented in Sections 5.3 and 5.4 and published in References [186] and [187] has been done on a device from this generation.
(d) A device with non-uniform bottom-gate structure and lead (Pb) superconducting electrode.
In a few devices the NW was cut with FIB milling in the middle, below the superconducting contact prior to Pb deposition (specifically, the sample in panel (d) is not cut). Preliminary measurement data acquired in such a FIB-cut CPSD with Pb superconductor is presented in Section 5.5.