The DAGs enable the processor to address memory indirectly

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Table 4-0.

Listing 4-0.

Maintaining pointers into memory, the processor’s two data address generators (DAGs) simplify the task of organizing data. The DAGs enable the processor to address memory indirectly; that is, an instruction specifies a DAG register that contains the address of a value instead of the value.

Data address generator 1 (DAG1) generates 32-bit addresses on the DM Address Bus. Data address generator 2 (DAG2) generates 24-bit addresses on the PM Address Bus. Figure 4-1 on page 4-3 shows the basic architecture of both DAGs. For details, see “Generating Addresses for the PM and DM Buses” on page 5-11.

The DAGs provide hardware support for some functions commonly used in digital signal processing algorithms. Both DAGs support circular data buffers, which require software to advance a pointer repetitively through a range of memory locations. Both DAGs can also perform a bit-reversing operation, which outputs the bits of an address in reversed order.

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Each DAG has four types of registers: Index (I), Modify (M), Base (B), and Length (L).

An I register acts as a pointer to memory, and an M register contains the value to increment the pointer. To vary the increment as needed, you modify an I register with different M values.

B and L registers work with circular data buffers only. These buffers oper- ate in pairs: B0 with L0, B4 with L4, B12 with L12, and so on. The B register holds the base address (first address) of a circular buffer. The corresponding L register contains the number of locations in the circular buffer, defining its length.

Each DAG contains eight of each register type, as shown in Table 4-1:

Table 4-1. DAG registers

DAG1 (32-bit) DAG2 (24-bit)

B0-B7 B8-B15

I0-I7 I8-I15

M0-M7 M8-M15

L0-L7 L8-L15

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Figure 4-1. Architecture of the data address generators (DAGs)

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To implement context switching, each DAG register has an alternate register. Figure 4-2 on page 4-4 shows how each DAG is organized into upper and lower halves for activating its alternate registers.

DM Data Bus

RegistersL 8xN

RegistersB 8xN

RegistersM 8xN

MUX

ADD RegistersI

8xN

MUX

Bit-Reverse

I0 (DAG1) / I8 (DAG2) only (optional)

PM Address Bus (DAG2) DM Address Bus (DAG1)

Update Bit-Reverse

(optional)

Modulus Logic

DAG1: N=32

DAG2: N=24 ²⁴ ₃₂

N N N

N

N N

N

N from

instruction

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Figure 4-2. Alternate DAG registers

The upper half of DAG1 contains I, M, B and L registers 4 through 7, and the lower half contains I, M, B and L registers 0 through 3.

Likewise, the upper half of DAG2 contains I, M, B and L registers 12 through 15, and the lower half contains I, M, B and L registers 8 through 11.

I0 I1 I2 I3

M0 M1 M2 M3

L0 L1 L2 L3

B0 B1 B2 B3 I4

I5 I6 I7

M4 M5 M6 M7

L4 L5 L6 L7

B4 B5 B6 B7

I8 I9 I10 I11

M8 M9 M10 M11

L8 L9 L10 L11

B8 B9 B10 B11 I12

I13 I14 I15

M12 M13 M14 M15

L12 L13 L14 L15

B12 B13 B14 B15 MODE1 Select Bit

SRD1L

SRD1H

SRD2L

SRD2H

DAG1 Registers (Data Memory)

DAG2 Registers (Program Memory)

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Table 4-2 shows the control bits in the MODE1 register that determine, for each half, whether the DAG’s primary or alternate registers are active:

This grouping of alternate registers enables you to pass pointers between contexts in each DAG.

Table 4-2. MODE1 DAG control bits for

Bit Name Definition

3 SRD1H DAG1 alternate register select (7-4) 4 SRD1L DAG1 alternate register select (3-0) 5 SRD2H DAG2 alternate register select (15-12) 6 SRD2L DAG2 alternate register select (11-8) 0 = primary registers; 1 = alternate registers

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DAG operations include:

• Address output with premodify or postmodify.

• Modulo addressing (for circular buffers).

• Bit-reversed addressing.

The DAGs right-shift short word addresses (16-bit data) by one bit before outputting them on the DM Address Bus. This enables internal memory to use the address directly. (For details, see “Using 16-Bit Short Word Accesses” on page 5-41.)

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The processor can generate addresses in one of two ways:

• Premodify operation

The processor adds an offset (modifier), either an M register or an immediate value, to an I register and outputs the resulting address.

This operation does not update the value of the I register.

Neither the L register nor modulo logic affect a premodified address.

Premodify addressing is always linear, never circular.

Restrictions on the use of premodify addressing operations may apply to some older silicon revisions. For details, see “Memory Organization” on page 5-16.

• Postmodify operation

The processor outputs the I register value as is and adds an M register or immediate value to form a new I register value.

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The width of an immediate modifier depends on the instruction. It can be as large as the width of the I register.

Figure 4-3 shows a comparison of the pre- and postmodify operations.

Figure 4-3. Comparison of premodify and postmodify operations '$*0RGLI\,QVWUXFWLRQV

In the processor’s assembly language, the positions of the index and modifier (M register or immediate value) in the instruction distinguishes the premodify and postmodify operations.

The I register coming before the modifier identifies the postmodify operation. Conversely, the modifier coming before the I register identifies the premodify with no update operation. For example, the following instruction accesses the program memory location with an address equal to the

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If you use postmodify addressing without implementing a circular buffer, make sure you set the corresponding L register to ⁰. Uninitialized L registers cause unpredictable postmodify behav- ior.

I

M

+

Output I+M

1. Output I

M I+M

+

2. Update PREMODIFY

no I register update POSTMODIFY I register update

PM(Ix, Mx) DM(Ix, Mx) PM(Mx, Ix)

DM(Mx, Ix)

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value stored in I15, and the processor writes back the value I15 + M12 to the I15 register:

R6 = PM(I15,M12); Indirect addressing with postmodify If the order in which the I and M registers appear in the instruction is reversed, the instruction accesses the location in program memory with an address equal to I15 + M12, but without changing the value of I15:

R6 = PM(M12,I15); Indirect addressing with premodify

Any M register can modify any I register within the same DAG (DAG1 or DAG2). So,

DM(M0,I2) = R0; valid instruction

DM(M0,I14) = R0; invalid instruction ,PPHGLDWH0RGLILHUV

The magnitude of an immediate value that can modify an I register depends on the instruction type and whether the I register is in DAG1 or in DAG2.

DAG1 modify values can be up to 32-bits wide. DAG2 modify values can be up to 24-bits wide. Some instructions with parallel operations support modify values up to 6-bits wide only. For example:

• 32-bit modifier

R1=DM(0x00400000,I1); DM address = I1 + 0x0040 0000

• 6-bit modifier:

F6=F1+F2,PM(I8,0x0B)=ASTAT; PM address = I8, I8 = I8 + 0x0B

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The DAGs provide addressing of locations within a circular data buffer.

A circular buffer consists of a set of memory locations that stores data and an index pointer that steps through the buffer. For each step, the processor postmodifies and updates the buffer’s I register by adding the value (positive or negative) specified in the M register to the value in the I register.

If the modified address pointer (M) falls outside the circular buffer, the processor either subtracts or adds, accordingly, the length of the buffer to the value to wrap the index pointer back to the start of the buffer (see Figure 4-4). The value of the base address of a circular buffer carries no restrictions.

Figure 4-4. Circular data buffers

For circular buffer addressing, you must use M registers to postmodify I registers, not to premodify them.

0 1 2 3 4 5 6 7 8 9 10

1

2

3

0 1 2 3 4 5 6 7 8 9 10

4

5

6

0 1 2 3 4 5 6 7 8 9 10

7

8

9

0 1 2 3 4 5 6 7 8 9 10

10

11

Sequence in order of locations accesed in one pass.

Sequence repeats on subsequent passes.

Length = 11 Base address = 0 Modifier = 4

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For example:

F1=DM(I0,M0);Use a postmodify operation to

modify circular buffers, not a premodify operation.

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To set up a circular buffer in assembly language, initialize an L register with a positive, nonzero value and load the corresponding B register with the base (starting) address of the buffer. The processor automatically loads the corresponding I register with this same starting address.

On the first postmodify access using the I register, the DAG outputs the I register value on the address bus and then modifies it by adding to it the value specified in the M register or an immediate value.

If the modified value is within the buffer’s range, the DAG writes it back to the I register. If the value is outside the buffer’s range, the DAG subtracts (or adds if the modify value is negative) the L register value to the modified value before writing the modified value back to the I register.

• If M is positive

I_QHZ=I_ROG + M If I_ROG+M < Buffer base + length (end of buffer)

I_QHZ=I_ROG + M–L If I_ROG+M ≥ Buffer base + length (end of buffer)

• If M is negative

I_QHZ=I_ROG + M If I_ROG+M ≥ Buffer base (start of buffer) I_QHZ=I_ROG + M + L If I_ROG+M < Buffer base

(start of buffer)

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A circular buffer uses all four types of DAG registers:

• The I register contains the value the processor outputs on the address bus.

• The M register contains the postmodify value (positive or negative) that the processor adds to the I register at the end of each memory access.

You can use any M register providing it is located in the same DAG as the I register. And you can use noncorresponding M and I register combinations; for example, registers M2 and I4.

You can use an immediate value or an M register value for the modifier. The magnitude of the modify value, whether from an M register or an immediate value, must be less than the length (L register) of the circular buffer.

• The L register sets the size of the circular buffer, defining the address range that the I register steps through.

The value of the L register must be positive and cannot have a value greater than 2³¹−1 (for L0 through L7) or 2²³ −1 (for L8 through L15). A value of 0 in an L register disables the circular buffer.

• After each access, the processor compares the modified I value to the B register value, or the sum of the B and L registers.

When the processor loads the B register, it also loads the corresponding I register with the same value. When it loads the I register,

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If you use postmodify addressing without implementing a circular buffer, make sure you set the corresponding L register to 0.

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it does not change the value in the B register. You can read the B and I registers independently.

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Circular buffer overflow interrupts are useful in implementing, for example, a ping-pong routine that swaps I/O buffer pointers.

One set of registers in each DAG can generate an interrupt when a circular buffer overflows (address wraparound occurs). In DAG1, the registers are B7, I7, and L7, and in DAG2, they are B15, I15, and L15.

A circular buffer addressing operation that uses these registers and causes the processor to increment or decrement the address in the I register past the end or start of the circular buffer generates an interrupt. Which interrupt is generated depends on the register set the operation used, as shown in Table 4-3.

Specifically, an instruction generates an interrupt during its address postmodify when:

(for M<0) I + M < B (for M≥0) I + M ≥ B + L

1 These symbols are defined in the #include file def21065L.h. For details, see Appendix E, Control and

Status Registers, in ADSP-21065L SHARC Technical Reference.

Table 4-3. Circular buffer overflow interrupts

Interrupt Use DAG… Vector Addr Symbolic

Name¹ DAG1 circular buffer 7

overflow

B7, I7, L7 0x54 CB7I

DAG2 circular buffer 15 overflow

B15, I15, L15 0x58 CB15I

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In certain situations, you may want to use I7 or I15 without circular buff- ering, but with the circular buffer overflow interrupts unmasked. To disable generation of these interrupts, set the B7 and B15 registers in DAG1 and the L7 and L15 registers in DAG2 to values that ensure the conditions that generate interrupts never occur. For example, when accessing the address range 0x1000 to 0x2000, set ^B=0x0000 and ^L=0xFFFF. (Setting the L register to zero (0) will not disable circular buffer interrupts.)

If you are using either of the circular buffer overflow interrupts, avoid using the corresponding I register(s) (I7 and I15) in the rest of your appli- cation software, or make sure your software sets the B and L registers accordingly to prevent spurious interrupt branching.

The STKY status register contains two bits that the processor sets when a circular buffer overflow occurs—bit 17 (DAG1 circular buffer 7 overflow) and bit 18 (DAG2 circular buffer 15 overflow). These bits are “sticky” and remain set until explicitly cleared.

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You can bit-reverse memory addresses two ways:

• Enabling bit-reverse mode on DAG1 or DAG2 and using a specific I register (I0 or I8).

• Using the explicit bit-reverse instruction BITREV.

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In bit reverse mode, DAG1 bit-reverses 32-bit address values output from I0, and DAG2 bit-reverses 24-bit address values output from I8.

The processor bit reverses the address values from the I0 and I8 registers only.

This mode affects both premodify and postmodify operations.

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The BR0 and BR8 bits in the MODE1 register enable these modes:

Bit reversal occurs at the output of the DAG and does not affect the value in I0 or I8. In postmodify operations, the processor does not bit reverse the update value.

For example:

I0=0x80400000;

R1=DM(I0,3); DM address=0x201, I0=0x80400003

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The BITREV instruction modifies and bit reverses addresses in any DAG index register (I0-I15), without actually accessing memory. This instruction operates independently of bit-reverse mode.

The BITREV instruction:

• Adds a 32-bit immediate value to a DAG1 index register. For a DAG2 index register, you can specify a zero immediate value only.

• Bit-reverses the result.

• Writes the result back to the same index register.

For example:

BITREV(I9,0); I9 = Bit-reverse of (I9+0)

Table 4-4. MODE1 bit reversal mode bits

Bit Name Description

0 BR8 Bit reverse mode for I8 (DAG2) 1 BR0 Bit reverse mode for I0 (DAG1)

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DAG registers are part of the universal register set. You can write to them from memory, from another universal register, or from an immediate field in an instruction. Conversely, you can write DAG register contents to memory or to a universal register.

As shown in Figure 4-5, transfers between 32-bit DAG1 registers and the 40-bit Data Memory Data (DMD) bus are aligned to bits 39:8 of the DMD bus.

Figure 4-5. DAG register transfers

When the processor reads 24-bit DAG2 registers over the 40-bit DMD bus, it sign-extends M register values to 32 bits and zero-fills I, L, and B register values to 32 bits. The results are aligned to bits 39:8 of the DMD Bus.

When the processor writes the DAG2 registers from the DMD bus, it transfers bits 31:8 and ignores the rest.

23 7 0

39

8 zeros 8 zeros

39 7 0

23 7 0

39

DAG2 M Register (15-8) 8 sign bits

8 zeros 8 zeros

DAG1 Register (7-0)

23 7 0

39

DAG2 M Register (15-8) DAG2 I, L, or B Reg. (15-8)

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For certain instruction sequences that involve transfers to and from DAG registers, the processor inserts a NOP cycle automatically.

Certain other sequences, which the assembler does not support, cause incorrect results:

• Instructions that generate an extra NOP cycle

The processor automatically inserts a NOP cycle between two con- secutive instructions if the first instruction loads a DAG register and the second instruction uses any register in the same DAG for data addressing, modify instructions, or indirect jumps.

The processor inserts the NOP instruction to delay the second operation since both operations need the same bus in the same cycle.

For example:

L2=8;

DM(I0,M1)=R1;

Because L2 is in the same DAG as I0 (and M1), the processor inserts an extra cycle after the write to L2.

• Illegal instructions that generate incorrect results

You can execute the following types of instructions on the processor, but they generate incorrect results and are unsupported:

• An instruction that uses indirect addressing from a DAG to store the same DAG register in memory, with or without updating the index register.

This instruction writes the wrong data to memory or updates the wrong index register.

For example: DM(M2,I1)=I0;orDM(I1,M2)=I0;

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• An instruction that uses indirect addressing from a DAG to load the same DAG register from memory and updates the index register.

This instruction either loads the DAG register or updates the index register, but not both.

For example: L2=DM(I1,M0);